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UNIXLIB37B
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_syslib
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1992-02-17
|
10KB
|
582 lines
; /* _syslib.s (c) Copyright 1990 H.Rogers */
a1 RN 0
a2 RN 1
a3 RN 2
a4 RN 3
v1 RN 4
v2 RN 5
v3 RN 6
v4 RN 7
v5 RN 8
v6 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lr RN 14
pc RN 15
f0 FN 0
f1 FN 1
f2 FN 2
f3 FN 3
f4 FN 4
f5 FN 5
f6 FN 6
f7 FN 7
AREA |C$$code|,CODE,READONLY
IMPORT |Image$$RO$$Base|
IMPORT |Image$$RW$$Limit|
EXPORT |__svccli| ; copy CLI in SVC mode
|__svccli|
LDR a2,[pc,#|__cli_ptr|-.-8]
LDR a2,[a2,#0]
MOV a4,lr
SWI &16 ; OS_EnterOS
|__svccli_l0|
LDRBT a3,[a2],#1
STRBT a3,[a1],#1
CMP a3,#0
BNE |__svccli_l0|
MOVS pc,a4 ; return to USR mode
|__cli_ptr|
DCD |__cli|
|__robase_ptr|
DCD |__robase|
|__base_ptr|
DCD |__base|
|__rwlimit_ptr|
DCD |__rwlimit|
|__himem_ptr|
DCD |__himem|
|__lomem_ptr|
DCD |__lomem|
|__break_ptr|
DCD |__break|
|__stack_ptr|
DCD |__stack|
|__time_ptr|
DCD |__time|
IMPORT |__alloca_list|,WEAK
|__alloca_list_ptr|
DCD |__alloca_list|
ENTRY
IMPORT |_main|
EXPORT |__main|
|__main|
SWI &20010 ; OS_GetEnv
MOV sp,a2
SUB sl,sp,#2048
LDR a4,[pc,#|__cli_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__himem_ptr|-.-8]
STR a2,[a4,#0]
LDR a4,[pc,#|__stack_ptr|-.-8]
STR sl,[a4,#0]
LDMIA a3,{a1,a2}
AND a2,a2,#&ff
LDR a3,[pc,#|__time_ptr|-.-8]
STMIA a3,{a1,a2}
LDR a4,[pc,#|__robase_ptr|-.-8]
LDR a1,[a4,#0]
LDR a4,[pc,#|__base_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__rwlimit_ptr|-.-8]
LDR a1,[a4,#0]
LDR a4,[pc,#|__lomem_ptr|-.-8]
STR a1,[a4,#0]
LDR a4,[pc,#|__break_ptr|-.-8]
STR a1,[a4,#0]
CMP sl,a1
MOVLSS pc,lr ; no stack - exit fast
ADD sl,sl,#256
MOV fp,#0
LDR a1,[pc,#|__alloca_list_ptr|-.-8]
CMP a1,#0
STRNE fp,[a1,#0]
B |_main|
EXPORT |__exit|
|__exit|
MOV a3,a1
LDR a2,[pc,#|__exit_word|-.-8]
MOV a1,#0
SWI &11 ; OS_Exit - never returns
|__exit_word|
DCD &58454241
IMPORT |__vret|,WEAK
EXPORT |___vret|
|___vret|
DCD |__vret|
IMPORT |__stdioinit|,WEAK
EXPORT |___stdioinit|
|___stdioinit|
DCD |__stdioinit|
IMPORT |__stdioexit|,WEAK
EXPORT |___stdioexit|
|___stdioexit|
DCD |__stdioexit|
EXPORT |__rdenv|
|__rdenv|
MOV ip,a2
MOV a2,#0
MOV a3,#0
MOV a4,#0
SWI &20040
STMVCIA ip,{a2,a3,a4}
MOVVC a1,#0
MOVS pc,lr
EXPORT |__wrenv|
|__wrenv|
LDMIA a2,{a2,a3,a4}
SWI &20040
MOVVC a1,#0
MOVS pc,lr
EXPORT |x$divtest|
|x$divtest|
MOVS pc,lr
EXPORT |x$remainder|
|x$remainder|
STMFD sp!,{lr}
BL |x$divide|
MOV a1,a2
LDMFD sp!,{pc}^
EXPORT |x$uremainder|
|x$uremainder|
STMFD sp!,{lr}
BL |x$udivide|
MOV a1,a2
LDMFD sp!,{pc}^
|x$overflow|
MVN a1,#0
MOVS pc,lr
EXPORT |x$udivide| ; a1 = a2 / a1; a2 = a2 % a1
|x$udivide|
CMP a1,#1
BLO |x$overflow|
BEQ |x$divide_l0|
MOV ip,#0
MOVS a2,a2
BPL |x$divide_l1|
ORR ip,ip,#&20000000; ip bit &20000000 = -ve a2
MOVS a2,a2,LSR #1
ORRCS ip,ip,#&10000000; ip bit &10000000 = bit 0 of a2
B |x$divide_l1|
|x$divide_l0| ; a1 == 1
MOV a1,a2
MOV a2,#0
MOVS pc,lr
EXPORT |x$divide| ; a1 = a2 / a1; a2 = a2 % a1
|x$divide|
CMP a1,#1
BLO |x$overflow|
BEQ |x$divide_l0|
ANDS ip,a1,#&80000000
RSBMI a1,a1,#0
ANDS a3,a2,#&80000000
EOR ip,ip,a3
RSBMI a2,a2,#0
ORR ip,a3,ip,LSR #1 ; ip bit &40000000 = -ve division
; ip bit &80000000 = -ve remainder
|x$divide_l1|
MOV a3,#1
MOV a4,#0
CMP a2,a1
BLO |x$divide_b0|
CMP a2,a1,LSL #1
BLO |x$divide_b1|
CMP a2,a1,LSL #2
BLO |x$divide_b2|
CMP a2,a1,LSL #3
BLO |x$divide_b3|
CMP a2,a1,LSL #4
BLO |x$divide_b4|
CMP a2,a1,LSL #5
BLO |x$divide_b5|
CMP a2,a1,LSL #6
BLO |x$divide_b6|
CMP a2,a1,LSL #7
BLO |x$divide_b7|
CMP a2,a1,LSL #8
BLO |x$divide_b8|
CMP a2,a1,LSL #9
BLO |x$divide_b9|
CMP a2,a1,LSL #10
BLO |x$divide_b10|
CMP a2,a1,LSL #11
BLO |x$divide_b11|
CMP a2,a1,LSL #12
BLO |x$divide_b12|
CMP a2,a1,LSL #13
BLO |x$divide_b13|
CMP a2,a1,LSL #14
BLO |x$divide_b14|
CMP a2,a1,LSL #15
BLO |x$divide_b15|
CMP a2,a1,LSL #16
BLO |x$divide_b16|
CMP a2,a1,LSL #17
BLO |x$divide_b17|
CMP a2,a1,LSL #18
BLO |x$divide_b18|
CMP a2,a1,LSL #19
BLO |x$divide_b19|
CMP a2,a1,LSL #20
BLO |x$divide_b20|
CMP a2,a1,LSL #21
BLO |x$divide_b21|
CMP a2,a1,LSL #22
BLO |x$divide_b22|
CMP a2,a1,LSL #23
BLO |x$divide_b23|
CMP a2,a1,LSL #24
BLO |x$divide_b24|
CMP a2,a1,LSL #25
BLO |x$divide_b25|
CMP a2,a1,LSL #26
BLO |x$divide_b26|
CMP a2,a1,LSL #27
BLO |x$divide_b27|
CMP a2,a1,LSL #28
BLO |x$divide_b28|
CMP a2,a1,LSL #29
BLO |x$divide_b29|
CMP a2,a1,LSL #30
BLO |x$divide_b30|
CMP a2,a1,LSL #31
SUBHS a2,a2,a1,LSL #31
ADDHS a4,a4,a3,LSL #31
CMP a2,a1,LSL #30
SUBHS a2,a2,a1,LSL #30
ADDHS a4,a4,a3,LSL #30
|x$divide_b30|
CMP a2,a1,LSL #29
SUBHS a2,a2,a1,LSL #29
ADDHS a4,a4,a3,LSL #29
|x$divide_b29|
CMP a2,a1,LSL #28
SUBHS a2,a2,a1,LSL #28
ADDHS a4,a4,a3,LSL #28
|x$divide_b28|
CMP a2,a1,LSL #27
SUBHSS a2,a2,a1,LSL #27
ADDHS a4,a4,a3,LSL #27
|x$divide_b27|
CMP a2,a1,LSL #26
SUBHS a2,a2,a1,LSL #26
ADDHS a4,a4,a3,LSL #26
|x$divide_b26|
CMP a2,a1,LSL #25
SUBHS a2,a2,a1,LSL #25
ADDHS a4,a4,a3,LSL #25
|x$divide_b25|
CMP a2,a1,LSL #24
SUBHS a2,a2,a1,LSL #24
ADDHS a4,a4,a3,LSL #24
|x$divide_b24|
CMP a2,a1,LSL #23
SUBHS a2,a2,a1,LSL #23
ADDHS a4,a4,a3,LSL #23
|x$divide_b23|
CMP a2,a1,LSL #22
SUBHS a2,a2,a1,LSL #22
ADDHS a4,a4,a3,LSL #22
|x$divide_b22|
CMP a2,a1,LSL #21
SUBHS a2,a2,a1,LSL #21
ADDHS a4,a4,a3,LSL #21
|x$divide_b21|
CMP a2,a1,LSL #20
SUBHS a2,a2,a1,LSL #20
ADDHS a4,a4,a3,LSL #20
|x$divide_b20|
CMP a2,a1,LSL #19
SUBHS a2,a2,a1,LSL #19
ADDHS a4,a4,a3,LSL #19
|x$divide_b19|
CMP a2,a1,LSL #18
SUBHS a2,a2,a1,LSL #18
ADDHS a4,a4,a3,LSL #18
|x$divide_b18|
CMP a2,a1,LSL #17
SUBHS a2,a2,a1,LSL #17
ADDHS a4,a4,a3,LSL #17
|x$divide_b17|
CMP a2,a1,LSL #16
SUBHS a2,a2,a1,LSL #16
ADDHS a4,a4,a3,LSL #16
|x$divide_b16|
CMP a2,a1,LSL #15
SUBHS a2,a2,a1,LSL #15
ADDHS a4,a4,a3,LSL #15
|x$divide_b15|
CMP a2,a1,LSL #14
SUBHS a2,a2,a1,LSL #14
ADDHS a4,a4,a3,LSL #14
|x$divide_b14|
CMP a2,a1,LSL #13
SUBHS a2,a2,a1,LSL #13
ADDHS a4,a4,a3,LSL #13
|x$divide_b13|
CMP a2,a1,LSL #12
SUBHS a2,a2,a1,LSL #12
ADDHS a4,a4,a3,LSL #12
|x$divide_b12|
CMP a2,a1,LSL #11
SUBHS a2,a2,a1,LSL #11
ADDHS a4,a4,a3,LSL #11
|x$divide_b11|
CMP a2,a1,LSL #10
SUBHS a2,a2,a1,LSL #10
ADDHS a4,a4,a3,LSL #10
|x$divide_b10|
CMP a2,a1,LSL #9
SUBHS a2,a2,a1,LSL #9
ADDHS a4,a4,a3,LSL #9
|x$divide_b9|
CMP a2,a1,LSL #8
SUBHS a2,a2,a1,LSL #8
ADDHS a4,a4,a3,LSL #8
|x$divide_b8|
CMP a2,a1,LSL #7
SUBHS a2,a2,a1,LSL #7
ADDHS a4,a4,a3,LSL #7
|x$divide_b7|
CMP a2,a1,LSL #6
SUBHS a2,a2,a1,LSL #6
ADDHS a4,a4,a3,LSL #6
|x$divide_b6|
CMP a2,a1,LSL #5
SUBHS a2,a2,a1,LSL #5
ADDHS a4,a4,a3,LSL #5
|x$divide_b5|
CMP a2,a1,LSL #4
SUBHS a2,a2,a1,LSL #4
ADDHS a4,a4,a3,LSL #4
|x$divide_b4|
CMP a2,a1,LSL #3
SUBHS a2,a2,a1,LSL #3
ADDHS a4,a4,a3,LSL #3
|x$divide_b3|
CMP a2,a1,LSL #2
SUBHS a2,a2,a1,LSL #2
ADDHS a4,a4,a3,LSL #2
|x$divide_b2|
CMP a2,a1,LSL #1
SUBHS a2,a2,a1,LSL #1
ADDHS a4,a4,a3,LSL #1
|x$divide_b1|
CMP a2,a1
SUBHS a2,a2,a1
ADDHS a4,a4,a3
|x$divide_b0|
TST ip,#&20000000
BNE |x$udivide_l1|
MOV a1,a4
CMP ip,#0
RSBMI a2,a2,#0
MOVS ip,ip,LSL #1
RSBMI a1,a1,#0
MOVS pc,lr
|x$udivide_l1|
TST ip,#&10000000
MOV a2,a2,LSL #1
ORRNE a2,a2,#1
MOV a4,a4,LSL #1
CMP a2,a1
SUBHS a2,a2,a1
ADDHS a4,a4,a3
MOV a1,a4
MOVS pc,lr
IMPORT raise
EXPORT |x$stack_overflow| ; allocate 512 bytes more stack
|x$stack_overflow|
STMFD sp!,{a1,a2,lr}
LDR a1,[pc,#|__break_ptr|-.-8]
LDR a1,[a1,#0]
LDR lr,[pc,#|__stack_ptr|-.-8]
LDR a2,[lr,#0]
SUB a2,a2,#512
CMP a2,a1
STR a2,[lr,#0]
ADD sl,a2,#256
LDMHIFD sp!,{a1,a2,pc}^
STMFD sp!,{a3,a4,ip}
MOV a1,#7 ; SIGEMT
BL raise
LDMFD sp!,{a3,a4,ip}
LDMFD sp!,{a1,a2,pc}^
EXPORT |x$stack_overflow_1| ; allocate stack to below <ip>
|x$stack_overflow_1|
CMP ip,sl ; sanity check
MOVHIS pc,lr
STMFD sp!,{a1,a2,lr}
LDR a1,[pc,#|__break_ptr|-.-8]
LDR a1,[a1,#0]
LDR lr,[pc,#|__stack_ptr|-.-8]
SUB a2,ip,#256
CMP a2,a1
STR a2,[lr,#0]
ADD sl,a2,#256
LDMHIFD sp!,{a1,a2,pc}^
STMFD sp!,{a3,a4,ip}
MOV a1,#7 ; SIGEMT
BL raise
LDMFD sp!,{a3,a4,ip}
LDMFD sp!,{a1,a2,pc}^
EXPORT |_wr1chk|
EXPORT |_wr2chk|
EXPORT |_wr4chk|
|_wr1chk|
|_wr2chk|
|_wr4chk|
LDR a2,[pc,#|__lomem_ptr|-.-8]
LDR a2,[a2,#0]
B |__rwNchk|
EXPORT |_rd1chk|
EXPORT |_rd2chk|
EXPORT |_rd4chk|
|_rd1chk|
|_rd2chk|
|_rd4chk|
LDR a2,[pc,#|__base_ptr|-.-8]
LDR a2,[a2,#0]
|__rwNchk|
CMP a1,a2
BLO |__rwNsegv|
LDR a2,[pc,#|__break_ptr|-.-8]
LDR a2,[a2,#0]
CMP a1,a2
MOVLOS pc,lr
LDR a2,[pc,#|__stack_ptr|-.-8]
LDR a2,[a2,#0]
CMP a1,a2
BLO |__rwNsegv|
LDR a2,[pc,#|__himem_ptr|-.-8]
LDR a2,[a2,#0]
CMP a1,a2
MOVLOS pc,lr
|__rwNsegv|
MOV a1,#11 ; SIGSEGV
B raise
EXPORT |_count|
|_count|
ADD lr,lr,#8
MOVS pc,lr
EXPORT |_count1|
|_count1|
ADD lr,lr,#8
MOVS pc,lr
AREA |C$$data|
EXPORT |__cli| ; CLI from OS_GetEnv
|__cli|
DCD 0
EXPORT |__base| ; BASE (application = 0x8000)
|__robase|
DCD |Image$$RO$$Base|
|__base|
DCD 0
EXPORT |__lomem| ; LOMEM
|__rwlimit|
DCD |Image$$RW$$Limit|
|__lomem|
DCD 0
EXPORT |__himem| ; HIMEM from OS_GetEnv
|__himem|
DCD 0
EXPORT |__break| ; the 'break'
|__break|
DCD 0
EXPORT |__stack| ; stack limit
|__stack|
DCD 0
EXPORT |__time| ; start time - 5 byte format
|__time|
DCD 0 ; low word
DCD 0 ; high byte
AREA |C$$wrcode|,CODE
EXPORT |__fptest|
|__fptest|
LDR a1,[pc,#|__fptest_l3|-.-8]
STR a1,[pc,#|__fptest_l1|-.-8]
B |__fptest_l1| ; clear pipeline
|__fptest_l1|
DCD 0
|__fptest_l2|
MOVS pc,lr
|__fptest_l3|
MVFD f0,f0
EXPORT |__fpclr|
|__fpclr|
MOV a1,#0
STR a1,[pc,#|__fpflag|-.-8]
LDR a1,[pc,#|__fptest_l2|-.-8]
STR a1,[pc,#|__fptest_l1|-.-8]
MOVS pc,lr
EXPORT |__fpflag|
|__fpflag|
DCD 0
END